Dual Rail Domino Logic

• Dual-rail domino gates encode each signal with a pair of wires. The input and output signal pairs are denoted with _h and _l, respectively.
• Table summarizes the encoding. The _h wire is asserted to indicate that the output of the gate is “high” or 1. The _l wire is asserted to indicate that the output of the gate is “low” or 0.
• When the gate is precharged, neither _h nor _l is asserted. The pair of lines should never be both asserted simultaneously during correct operation

Dual-rail domino signal encoding

• Dual-rail domino gates accept both true and complementary inputs and compute both true and complementary outputs, as shown in Figure (a).
• This is identical to static CVSL circuits except that the cross-coupled pMOS transistors are instead connected to the precharge clock.
• Therefore, dual-rail domino can be viewed as a dynamic form of CVSL, sometimes called DCVS.
• Figure (b) shows a dual-rail AND/NAND gate and Figure (c) shows a dual-rail XOR/XNOR gate. The gates are shown with clocked evaluation transistors, but can also be unfooted.

Dual-rail domino gates

Disadvantages:

• It requires more area, wiring and power.
• Dual-rail structures lose the efficiency of wide dynamic NOR gates.

Application:

• It is useful for asynchronous circuits.