Double Pass Transistor Logic (DPL)

• Double Pass Transistor Logic is a double rail form of CMOS transmission gate optimized to use single pass transistors where only a known 0 or 1 needs to be passed.
• It passes good high and low logic levels without the need for level restoring devices.
• DPL uses both nMOS and pMOS switches to realize the desired functions.
• This provides a full swing on the output.
• No extra transistors are required for swing restoration.
• A DPL gate consists of both true and complementary inputs / outputs and hence is a dual rail logic circuit.

Synthesis Rules

• Two NMOS branches cannot be overlapped covering logic 1s. Similarly, two PMOS branches cannot be overlapped covering logic 0s.
• Pass signals are expressed in terms of input signals or supply. Every input vector has to be covered with exactly two branches.
• At any time, excluding transitions, exactly two transistor branches are active (any of the pairs NMOS/PMOS, NMOS/NMOS and PMOS/PMOS are possible), i.e. they both provide output current.

Complementary Principle: Complementary logic function in DPL is generated after the following modifications:

• Exchange PMOS and NMOS devices. Invert all pass and gate signals

Duality Principle: Dual logic function in DPL is generated when:

• PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged.