Differential Pass Transistor Logic / Complementary Pass Transistor Logic (CPL)

• For high performance design, a differential pass-transistor logic family, called CPL, is commonly used.
• The basic idea is to accept true and complementary inputs and produce true and complementary outputs.
• A number of CPL gates (AND/NAND, OR/NOR, and XOR/NXOR) are shown in Figure.
• Since the circuits are differential, complementary data inputs and outputs are always available.
• Both polarities of every signal eliminate the need for extra inverters, as is often the case in static CMOS or pseudo-NMOS.
• CPL belongs to the class of static gates, because the output-defining nodes are always connected to either VDD or GND through a low resistance path.
• This is advantage for the noise flexibility.

Formal Method for CPL Logic Derivation (AND, NAND, OR, NOR)

(a) Cover the Karnaugh-map with largest possible cubes (overlapping allowed)

(b) Express the value of the function in each cube in terms of input signals.

(c) Assign one branch of transistor(s) to each of the cubes and connect all the branches to one.