Layout Design Rules and Gate Layouts

• Draw and explain briefly the n-well CMOS design rules. 

• Discuss in detail with a neat layout, the design rules for a CMOS inverter.

• Write the layout design rules and draw diagram for four input NAND and NOR. 

• State the minimum width and minimum spacing lambda based design rules to draw the layout.

1. Layout rules also referred to as design rules.
2. It can be considered as prescription for preparing the photomasks, which are used in the fabrication of integrated circuits.
3. The rules are defined in terms of feature sizes (widths), separations and overlaps.
4. The main objective of the layout rules is to build reliable functional circuits in as small area as possible.
5. Layout design rules describe how small features can be and how closely they can be reliably packed in a particular manufacturing process.
6. Design rules are a set of geometrical specifications that dictate the design of the layout masks.
7. A design rule set provides numerical values for minimum dimensions and line spacing.
8. Scalable design rules are based on a single parameter (λ), which characterizes the resolution of the process. λ is generally half of the minimum drawn transistor channel length.
9. This length is the distance between the source and drain of a transistor and is set by the minimum width of a polysilicon wire.

Lambda based rule (Scalable design rule):

• Lambda-based rules are round up dimensions of scaling to an integer multiple of λ.
• Lambda rules make scaling layout small. The same layout can be moved to a new process, simply by specifying a new value of λ.
• The minimum feature size of a technology is characterized as 2λ.

Micron Design Rules (Absolute dimensions):

• The MOSIS rules are expressed in terms of lambda.
• These rules allow some degree of scaling between processes.
• Only need to reduce the value of lambda and the designs will be valid in the next process down in size.
• These processes rarely shrink uniformly.
• Thus, industry usually uses the actual micron design rules for layouts.
• There are set of micron design rules for a hypothetical 65 nm process.
• We can observe that, these rules differ slightly but not immensely from lambda based rules with lambda = 0.035 micro meter.
• Upper level metal rules are highly variable depending on the metal thickness. Thicker wires require greater widths, spacing and bigger vias. 

Two metal layers in an n-well process has the following:

• Metal and diffusion have minimum width and spacing of 4 λ.
• Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on the layers above and below.
• Polysilicon uses a width of 2 λ.
• Polysilicon overlaps diffusion by 2 λ where a transistor is desired and has a spacing of 1 λ away where no transistor is desired.
• Polysilicon and contacts have spacing of 3 λ from other polysilicon or contacts.
• N-well surrounds pMOS transistors by 6 λ and avoids nMOS transistors by 6 λ.

Simplified λ -based design rules with CMOS inverter layout diagram

Design Rule:

Well Rules:

• The n-well is usually a deeper implant than the transistor source/drain implants.
• Therefore, it is necessary to provide sufficient clearance between the n-well edges and the adjacent n+ diffusions. 

Transistor Rules:

• CMOS transistors are generally defined by at least four physical masks.
• There are active (also called diffusion, diff, thinox, OD, or RX), n-select (also called nimplant, n-imp, or nplus), p-select (also called p-implant, pimp, or pplus) and polysilicon (also called poly, polyg, PO, or PC).
• The active mask defines all areas, where n- or p-type diffusion is to be placed or where the gates of transistor are to be placed.

Contact Rules:

1. There are several generally available contacts:
2. Metal to p-active (p-diffusion)
3. Metal to n-active (n-diffusion)
4. Metal to polysilicon
5. Metal to well or substrate

Metal Rules:

• Metal spacing may vary with the width of the metal line.
• Metal wire width of minimum spacing may be increased. This is due to etch characteristics versus large metal wires. 

Via Rules:

• Processes may allow vias to be placed over polysilicon and diffusion regions.
• Some processes allow vias to be placed within these areas, but do not allow the vias to the boundary of polysilicon or diffusion.

Example: NAND3

Draw the gate layout diagram of NAND. 

Horizontal N-diffusion and p-diffusion strips

Vertical polysilicon gates

Metal1 VDD rail at top

Metal1 GND rail at bottom

Draw diagram for four input NAND and NOR gate