Methods of reducing static power

Power gating:

• To reduce static current during sleep mode is, to turn OFF the power supply to the sleeping blocks. This technique is called power gating.

power gating

• The logic block receives its power from a virtual VDD rail, VDDV.
• When the block is active, the header switch transistors are ON, connecting VDDV to VDD.
• When the block goes to sleep, the header switch turns OFF, allowing VDDV to float and gradually sink toward 0.

Multiple threshold voltage and oxide thickness:

• Selective application of multiple threshold voltages can maintain performance on
• critical paths with low-Vt transistors, while reducing leakage on other paths with highVt transistors.

Variable threshold voltage:

• Method to achieve high Ion in active mode and low Ioff in sleep mode is, by adjusting the threshold voltage of the transistor by applying a body bias.
• This technique is sometimes called variable threshold CMOS (VTCMOS).
• Figure shows a schematic of an inverter using body bias.