SCALING

Discuss the scaling principles and its limits. (MAY 2013, Nov 2017, Nov 2018)
Discuss the principle of constant field and lateral scaling. Write the effects of the above scaling methods on the device characteristics. (Nov 2012, Dec 2011, Nov 2015, May 2016)
Explain need of scaling, scaling principles and fundamental units of CMOS inverter. (May 2017)
Highlight the need for scaling. Enumerate in detail constant electric field, constant voltage and combined electric field and voltage scaling for different parameters of MOSFET. [Nov 2019]

1. In VLSI design, the transistor size has reduced by 30% every two to three years. Scaling is reducing feature size of transistor.
2. Nowadays, transistors become smaller, switch faster, dissipate less power and cheaper.
3. Designers need to predict the effect of feature size scaling on chip performance to plan future products and ensure existing products for cost reduction.

Transistor scaling:

1.  Dennard’s Scaling Law predicts that the basic operational characteristics of a MOS transistor can be preserved and the performance can be improved.
2.  Parameters of a device are scaled by a dimensionless factor S.

 These parameters include the following:

• All dimensions (in the x, y, and z directions)
•  Device voltages
•  Doping concentration densities.

Constant field scaling (Full Scaling):

1.  In constant field scaling, electric fields remain the same as both voltage and distance shrink.
2.  1/S scaling is applied to all dimensions, device voltages and concentration densities.

•  Ids per transistor are scaled by 1/S.
•  No. of transistors per unit area is scaled by S2.
•  Current density is scaled by S and power density remains constant.

Lateral scaling (gate-shrink):

 Another approach is lateral scaling, in which only the gate length is scaled. 

 This is commonly called as gate shrink, because it can be done easily to an existing mask database for a design.

•  Ids per transistor are scaled by S.
•  No. of transistors per unit area is scaled by S.
•  Current density is scaled by S2 and power density is scaled by S2

 The industry generally scales process generations with 30% shrink.

 It reduces the cost (area) of a transistor by a factor of two.

 A 5% gate shrink (S = 1.05) is commonly applied as a process, becomes mature to boost the speed of components in that process.

• Constant voltage scaling: V DD is held constant, while process is scaled.
•  Constant voltage scaling (Fixed scaling) offers quadratic delay improvement as well as cost reduction.
•  It is also maintaining continuity in I/O voltage standards. Constant voltage scaling increases the electric fields in devices.
•  Ids per transistor are scaled by S.
•  No. of transistors per unit area is scaled by S2
•  Current density is scaled by S3 and power density is scaled by S3
•  A 30% shrink with Dennard scaling improves clock frequency by 40% and cuts power consumption per gate by a factor of 2.
•  Maintaining a constant field has the further benefit, that many nonlinear factors and wear out mechanisms are unaffected.
•  From 90nm generation technology, voltage scaling is dramatically slowed down due to leakage. This may ultimately limit CMOS scaling.

Interconnecting Scaling:

• Wires to be scaled equally in width and thickness to maintain an aspect ratio close to 2.
•  Wires can be classified as local, semiglobal and global.
•  Local wires run within functional units and use the bottom layers of metal.
•  Semiglobal wires run across larger blocks or cores, typically using middle layers of metal.
•  Both local and semiglobal wires are scaling with feature size.
•  Global wires run across the entire chip using upper levels of metal.
•  Global wires do not scale with feature size. Indeed, they may get longer (by a factor of DC, on the order of 1.1) because, die size has been gradually increasing.
•  When wire thickness is scaled, the capacitance per unit length remains constant.