VLSI AND CHIP DESIGN TWO MARKS SHORT QUESTIONS & ANSWERS
VLSI AND CHIP DESIGN TWO MARKS SHORT QUESTIONS & ANSWERS
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| VLSI AND CHIP DESIGN TWO MARKS SHORT QUESTIONS & ANSWERS |
UNIT I - MOS TRANSISTOR PRINCIPLES
1. Give the advantages of Integrated Circuit.
2. What is meant by CMOS technology?
3. How do you construct MOS transistor?
4. What is meant by MOS transistor?
6. Draw the schematic structure of n-MOS and p-MOS transistor with symbol.
8. Compare nMOS and pMOS devices. (or) How CMOS act as a switch?
9. Compare depletion and enhancement mode devices.
10. Why nMOS technology is preferred more than pMOS technology?
11. Define threshold voltage of MOSFET
14. What is meant by accumulation mode in MOS transistor?
15. What is meant by depletion mode in MOS transistor?
16. What is meant by inversion mode (or) inversion layer in MOS transistor?
17. List the different operating regions of MOS system.
18. When the channel is said to be pinched –off?
19. When will nMOS transistor operates in cutoff region?
20. When will nMOS transistor operates in linear region?
21. When will nMOS transistor operates in saturation region?
23. Give the expression for drain current (Ids) for different modes of operation of MOS transistor.
24. List the different capacitances of a MOS transistor.
25. Define body effect (or) substrate bias effect
26. Draw the I-V characteristics of MOS transistor
27. What are the secondary effects (or ) Non ideal effects of MOS transistor?
28. What is velocity saturation effect?
29. Define channel length modulation
30. What is body effect coefficient?
31. What do you mean by propagation delay time?
32. Draw the circuit of a CMOS inverter
33. What are the advantages of CMOS inverter over the other inverter configurations?
34. Draw the DC transfer characteristics of CMOS inverter.
36. What are the steps involved in the process of IC fabrication?
37. What are the different fabrication processes available to CMOS technology?
38. What is twin-tub process? Why it is called so?
39. What do you mean by lateral scaling?
41. List different types of scaling.
42. What are the advantages of scaling?
43. What is the influence of voltage scaling on power and delay?
44. List out the limitations of the constant voltage scaling.
45. Define SSI, MSI, LSI and VLSI.
46. Give objective of layout design rule.
47. Give propagation delay expression of CMOS inverter
48. Why NMOS device conducts strong zero and weak one?
49. By What factor RDS should be scaled, if constant electric filed scaling is employed?
50. List the scaling principles.
51. Why nMOS transistor is selected as pull down transistor?
52. Name the merits of Scaling Principles.
53. What is meant channel length modulation in NMOS transistor?
54. What are the different layers in MOS transistor?
55. What are the different operating regions for an MOS transistor?
56. What is Enhancement mode transistor?
57. What is Depletion mode device?
58. When the channel is said to be pinched off?
59. What are the steps involved in manufacturing of IC?
61. What are the processes involved in photo lithography?
62. What is the purpose of masking in fabrication of IC?
63. What are the materials used for masking?
64. What are the types of Photo etching?
65. What is diffusion process? What are doping impurities?
66. What is Ion Implantation process?
67. What are the various Silicon wafer Preparation?
68. What are the different types of oxidation?
70. Give the different types of CMOS process.
71. What is Channel stop Implantation?
75. What is Twin tub process? Why it is called so?
76. What are the steps involved in Twin tub process?
77. Name the special features of Twin tub process.
78. List out the advantages of Twin tub process?
79. What is SOI? What is the material used as Insulator?
80. What are the advantages and disadvantages of SOI process?
81. What are the advantages of CMOS process?
82. Define Short Channel devices.
83. What are the advantages of Silicon-on-Insulator process?
84. What are the advantages of CMOS process?
85. What is the fundamental goal in Device modeling?
87. Give the advantages of CMOS IC?
88. What are four generations of Integration Circuits?
89. Give the variety of Integrated Circuits.
90. Why NMOS technology is preferred more than PMOS technology?
UNIT II - COMBINATIONAL LOGIC CIRCUITS
1. Define combinational circuit and give an example.
2. Define sequential circuit and give an example.
3. What is the static CMOS inverter?
4. What are the advantages of static CMOS circuits?
5. What are the disadvantages of static CMOS circuits?
6. What is bubble pushing?
7. What is meant by compound gate?
8. What is the function of skewed gate?
9. What are the types of skewed gate?
10. Define P/N ratio.
11. What is meant by ratioed logic?
12. What is meant by pseudo nMOS logic?
13. Draw a pseudo nMOS inverter.
14. What are the disadvantages of using a pseudo nMOS gate instead of a full CMOS gate?
15. What are advantages and disadvantages of ratioed logic?
16. Compare CMOS combinational logic gates with reference to the equivalent nMOS depletion load logic with reference to the area requirement.
17. What is AOI logic function?
18. What is AOI 221 Gate?
19. What is meant by Asymmetric Gates?
20. What is meant by Cascode Voltage Switch Logic?
21. What are the advantages of Cascode Voltage Switch Logic?
22. Define rise & fall time.
23. What is edge rate?
24. What do you mean by propagation delay time?
25. What do you mean by contamination delay time?
26. What is meant by average contamination delay time?
27. What is meant by RC delay model?
28. Draw equivalent RC delay model for a MOS transistor?
29. Define electrical or fanout.
30. What is parasitic delay?
31.Write the general expression of parasitic delay for n inputs NAND and NOR gate?
32. Write the expression for the logical effort and parasitic delay of n input NOR gate.
33. What is meant by dynamic logic?
34. What are the two modes of operation in dynamic logic and give its functions?
35. What are the disadvantages of dynamic logic?
36. What are the advantages of dynamic logic?
37. What is the use of footed transistor in dynamic logic circuit?
38. What is meant by Monotonicity problem?
39. What is meant by domino logic?
40. Write the features of CMOS Domino Logic?
41. What is the use of keeper circuit?
42. What is meant by pass transistors?43. Which MOS can pass logic 1 and logic 0 strongly?
44. What is meant by CMOS Transmission gate? (Nov 2007, May 2011)(or) Define Transmission gate.
45. State the advantages of Transmission gate.
46. Draw the CMOS implementation of 4-to-1 MUX using transmission gates.
47. What are the various forms of inverter based CMOS logic?
48. Draw 2:1 MUX using transmission gate.
49. Draw XOR and XNOR using transmission gates.
50. Draw a two input XOR using nMOS pass transistor logic.
51. Define power dissipation.
52. List the types of power dissipation.
53. What do you understand by static & dynamic power dissipation?
54. What do you mean by low power design?
55. What are the factors that cause dynamic power dissipation in CMOS circuits?
56. How can dynamic power dissipation reduced? (or) State any two criteria for low power logic design.
57. Write the expression for power dissipation in CMOS inverter.
58. What are the factors that cause static power dissipation in CMOS circuits?
List the sources of static power consumption.
59. How can static power dissipation reduced?
60. Why single phase dynamic logic structure cannot be cascaded? Justify.
61. What is Complementary Pass Transistor logic?
62. Give the effects of supply voltage and temperature variations CMOS circuits.
63. Implement a 2:1 multiplexer using pass transistor.
64. Compare static and dynamic power dissipation.
65. What is the value of Vout for the figure shown below, where Vtn is threshold voltage of transistor?
66. How does a transmission gate produce fully restored logic output?
67. What is charge sharing in dynamic CMOS logic?
68. What is use of transmission gates?
69. List the sources of power dissipation in CMOS circuits.
70. List out the advantages and disadvantages of Pass Transistor Logic.
71. List any two types of layout design rules.
72. What are design rules? What is the need for design rules?
73. Define the lambda layout rules. What is meant by lambda layout design rules?
Discuss any two layout design rules.
74. By what factor, gate capacitance must be scaled if constant electric field scaling is employed?
75. What are stick diagrams?
76. What are the uses of Stick diagram?
77. Give the various color coding used in stick diagram?
78. Why does interconnect increase the circuit delay?
79. What is transistor sizing problem?
80. What is CMOS latchup? How do you prevent Latch up problem? (Nov 2008) (or) What is Latch up problem in CMOS circuits?
81. What is BiCMOS Gate? Compare CMOS and BiCMOS technology.
82. What is the need of demarcation line?
83. Draw the stick diagram and layout for CMOS inverter
84. Draw the stick diagram of static CMOS 2-input NAND gate
85. What are simulations available for VLSI circuits?
86. Why nMOS transistor is selected as pull down network?
87. Draw the stick diagram of NMOS NOR gate.
88. How do you describe the term device modeling?
89. What is Elmore’s delay model? (or) Give the expression for Elmore delay and state the various parameters associated with it.
90. Define logical effort and give logical effort value of inverter.
91.Write the general expression of logical effort for n inputs NAND and NOR
gate?
92. Draw a 2- input CMOS NOR Gate.
93. Write the expression for parasitic delay and logical effort of an N-input NAND gate.
94. Sketch a complementary CMOS gate computing W = (XY+YZ)’.Sketch a complementary CMOS gate computing Y = (AB+BC)’.
95. What is body effect.
96. What is velocity saturation effect?
97. Define propagation delay of a CMOS inverter.
98. Why NMOS device conducts strong zero and weak one?
99. What is Intrinsic and Extrinsic Semiconductor?
100.State the channel length modulation. Write the equation for describing channel length modulation effect in NMOS transistor.
101.What is latch up? How is Prevent latch up?
102.What are the different MOS layers?
103. If two CMOS inverters are cascaded with an aspect ratio of 1:1 then determine the inverter pair delay.
104. Differentiate static and dynamic latches and registers.Difference between Static latches & registers and Dynamic latches & registers.
UNIT – III
SEQUENTIAL LOGIC CIRCUITS AND CLOCKING STRATEGIES
1. What is a Sequential circuit?
2. What are sequencing methods available in sequential circuit design?
3. What is meant by maximum delay or setup time failure and how to avoid?
4. Define sequencing overhead.
5. What is meant by Min-delay failure and how to avoid?
6. Define time borrowing.
7. Define clock skew.
8. How to design CMOS flip-flop?
9. How to design Semidynamic Flip-flop?
10. What is meant by semidynamic flip-flop(SDFF)?
11. What is meant by Differential flip-flop?
12. What is meant by True Single Phase Clock (TSPC) Latch or flip-flop?
13. What are sequencing dynamic circuits?
14. Define Synchronizer.
15. What is a Latch?
16. What is a flip-flop?
17. What is meant by Bistability and metastability?
18. Define aperture.
19. How to design simple synchronizer circuit.
20. What is meant by Arbiter?
21. What are the advantages of differential Flip flop?
22. State the reasons for the speed advantages of CVSL family.
23. Enumerate the features of synchronizers.
24. What are the disadvantages of using a pseudo nMOS gate instead of a full CMOS gate?
25. What is Klass-semidynamic flip-flop?
26. What are the different phases of VLSI design flow?
27. Draw the circuit diagram of a CMOS bistable element and its time domain behavior.
28. What is CMOS clocked SR flipflop?
29. What do mean by multiplexer based latches?
30. What is Master-Slave Based Edge Triggered Register?
31. What is the advantage of multiplexer based latch?
32. What is pseudostatic?
33. What is called Clocked CMOS Register?
34. What is meant by Dual-edge Triggered Register? Give it advantage
35. What is True Single-Phase Clocked Register (TSPCR)?
36. What is the advantage and disadvantage of True Single-phase clocked register?
37. What is pipelining?
38. What is necessary of non-overlapping clocks?
39. What is topology for NORA-CMOS?
40. Tabulate the operation modules of NORA-CMOS circuit.
41. Define the dynamic-logic rule.
42. Define C2MOS design rule.
43. Draw the switch level schematic of multiplexer
44. What is known as H-tree clock distribution?
45. Define clock jitter.
46. What is meant by Latch based clocking?
47. Compare synchronous and asynchronous design. (
48. Define Set up time and hold time.
49. Draw the circuit and wave form for Pulse Registers
50. Define Pulse Registers
51. List the advantage and disadvantage of Pulse Registers
52. What is Sense – Amplifier Based Registers?
53. Draw the circuit of Sense – Amplifier Based Registers.
54. Differentiate between latch and flip-flop.Compare register and latch.
55. Define Schmitt trigger.
56. Draw the symbol, circuit and voltage transfer characteristics of Schmitt trigger.
57. Define Astable sequential circuits. Draw the circuit also.
58. Define Monostable sequential circuits.
59. State the use of Schmitt trigger
60. Draw a MUX based negative level sensitive D-latch.
61. List the timing classification of Digital system.
UNIT – IV
INTERCONNECT, MEMORY ARCHITECTURE AND ARITHMETICCIRCUITS
1. What is meant by data path circuits?
2. What is ripple carry adder?
3. Draw the circuit for 4 bit ripple carry adder.
4. Write the equation for total delay in 4 bit ripple carry adder.
5. Write the equation for worst case delay in 4 bit ripple carry adder
6. What is meant by Carry Lookahead Adder (CLA)?
7. Write the general expression for carry signal in CLA.Write the full adder output interms of propagate and generate.
8. Write the equation for generate term in CLA.
9. Write the equation for propagates term in CLA.
10. What are the two factors that Carry lookahead adder depends on?
11. Write the generalized equation for CLA
12. Name the limitations of MODL
13. What is called Manchester Carry Chain Adder?
14. Write the basic equation for Manchester Carry Chain Adder? Define kill term, propagate and generate term in a carry look ahead adder.
15. Draw the switch level circuit for Manchester carry chain adder.
16. What are high (wide) adders?
17. What are the types of high speed adders?
18. What is Carry skip adder?
19. What is Carry Select adder?
20. What is Carry save adder?
21. What are accumulators?
22. What are multipliers?
23. Draw the truth table of multiplier
24. Mention the steps involved in multiplying by shifting.
25. Write the delay equation for array multiplier
26. State radix-2 booth encoding table.
27. What is meant by divider circuit?
28. What are the types of dividers available in VLSI?
29. Compare serial divider and parallel divider
30. What is shift register?
31. What is meant by Barrel shifter?
32. Draw the structure of 4 X 4 barrel shifter.
33. What is the area constraint between carry lookahead adder and ripple carry adder?
34. What is the drawback of carry lookahead adder?
35. Draw the graph between area Vs delay of carry lookahead and ripple carry adder for 8 bit
36. Draw the graph between area Vs delay of carry lookahead and ripple carry adder for 16 bit.
37. Draw the graph between area Vs delay of carry lookahead and ripple carry adder for32 bit.
38. What is meant by bit – sliced data path organization?
39. Determine propagation delay of n-bit carry select adder.
40. Draw and list out the components of data path.
41. Mention the application of Barrel shift register. Why is barrel shifter very useful in the designing of arithmetic circuits?
42. What is latency?
43. Give the applications of high speed adder.
44. What is meant by booth multiplier?
45. What is meant by array multiplier?
46. What is Wallace tree multiplier? And give its advantages.
47. What are parameters used to characterize the memory?
48. How can you classify memory based on operation mode?
49. How can you classify memory based on data storage mode?
50. Define ROM. Give some examples.
51. What are advantage and disadvantages of programming ROM?
52. What is meant by non-volatile memory?
53. What is floating gate transistor?
54. What is RAM? And give types of RAM.
55. Distinguish Static and dynamic RAM
56. Draw the schematic of dynamic edge –triggered register.
57. Design a one transistor DRAM cell.
58. Design a three transistors DRAM cell.
59. State the merits of barrel shifter
60. How to design a high speed adder?
61. Mention the different hardware architecture used for multiplier.
62. Draw the dot diagram for Wallace tree multiplier.
63. List the categories of memory arrays.
64. State the need of a sense amplifier in a memory cell.
65. What are the building blocks of digital architecture?
66. Mention the steps for single bit addition.
UNIT V - ASIC DESIGN AND TESTING
1. List out the Implementation technologies in ASIC.
2. What are the types of ASICs?
3. What is meant by Full-Custom design?
4. What are the features of Full-Custom ASICs?
5. What are the disadvantages of Full-Custom ASICs?
6. Give examples of Full-Custom ASICs
7. What are Semi-custom ASICs?
8. What is meant by standard cell?
9. What is the standard cell-based ASIC design?
10. What is meant by CBIC?
11. What is Channeled Gate Array?
12. What is Channel less Gate Array?
13. What is Structured Gate Array?
14. What is Ratio factor?
15. Write the Goals and Objectives of floor planning?
16. What is Channel Definition?
17. What is placement?
18. What are the different placement algorithms in ASIC
19. What is synthesis?
20. What is Timing-driven placement?
21. What is Routing?
22. What are the two different types of routing?
23. What is Global Routing?
24. What are the methods of Global Routing?
25. What is hierarchical routing?
26. What is Reserved-layer routing?
27. What is Special Routing?
28. What is meant by standard cell library? What is the role of cell libraries in ASIC design?
29. What are the models should have in a cell library?
30. What is meant by library cell design?
31. List out the basic elements of the FPGA structure. State the three important blocks in FPGA architecture.State the building blocks of FPGA.
32. Name the elements in a Configuration Logic Block.
33. Write the features of Xilinx FPGA.
34. Give the functions of Input Output Block.
35. Write about various ways of routing procedure.
36. What is VLSI and ULSI?
37. What is feed through cells? State their uses.
38. What is a programmable logic device?
39. What are the types of programmable logic device (Programmable ASIC)?
40. What is meant by ASIC?
41. What is an antifuse? State its merits and demerits.
42. What is PLA?
43. What is PAL?
44. What are the types FPGA programming technologies? What are the different types of programming structure available in PAL?
45. What is meant by Reprogrammable Gate array (FPGA)? What is the significance of field programmable gate arrays?
46. Differentiate between Full custom and Cell based ASICs.
47. What is needed for testing?
48. What are different stages of testing on a chip?
49. What is meant by tester in VLSI testing?
50. Distinguish testers and test fixtures
51. State all the test vectors to test 3 input NAND gate.
52. What are the test fixtures required to test a chips?
53. What is meant by test program?
54. What is handler?
55. How is testing classified? List out the basic types of CMOS testing (or) What are the different types of CMOS testing?
56. What is functionality test? State the objective of functionality test.
57. What is manufacturability test?
58. Distinguish functionality test and manufacturing test.
59. What is the principle behind logic verification?
60. Define test benches and harness.
61. What is shmooing?
62. What is shmooing plots?
63. What is VCD?
64. What is version control?
65. What is regression testing?
66. What is meant by Bug tracking?
67. What is meant by silicon debugging principles and name some probes used for it?
68. What is hotspot and how it is examined?
69. How the temperature is examined in a chip?
70. What is FIB?
71. What is electrical failure?
72. What is struck at fault?
73. What is struck open fault?
74. What is bridging fault or short circuit fault?
75. List any two faults that occur during manufacturing.
76. Define fault coverage?
77. How is the bridging fault categorized?
78. What is observability?
79. What is controllability?
80. What is meant by ATPG?
81. What are the 3 approaches in design for testability? (or) List out design required for testing in CMOS chip design.
82. What do you mean by DFT?
83. What is serial scan & parallel scan?
84. List the common techniques for ad hoc testing.
85. What is signature analyzer?
86. What is the drawback of scan based approaches?
87. What is the aim of Adhoc test techniques?
88. What is the MUX test technique?
89. Write a note on partition and MUX technique.What are common techniques used in adhoc testing?
90. What are scannable elements for circuit design?
91. What is the necessary for non-overlapping clocks?
92. What is syndrome?
93. What is LSSD?
94. What is BIST or BILBO?
95. What is needed for IDDQ testing?
96. What are the limitations of IDDQ testing?
97. What is meant by system level (Boundary scan) testing?
98. Draw the boundary scan input logic diagram.
99. What is TAP?
100. What are the signals used in Tap Access port (TAP)?
101.Draw the Tap Access port (TAP) architecture.
102.What is meant by TAP controller?
103.What is bypass register?
104.What is instruction register?
105.What is Data Register (DR)?
106. What is boundary scan register?
107.What are logic verification principles?
106.Compare full custom and semi-custom design
107.Identify the ways to optimize the manufacturability, to increase yield.
108.What are the advantages and disadvantages of BIST?
109.What is configurable logic block meant?
