VLSI AND CHIP DESIGN Notes

VLSI AND CHIP DESIGN Notes

VLSI AND CHIP DESIGN Notes

UNIT I - MOS TRANSISTOR PRINCIPLES

MOS logic families (NMOS and CMOS), Ideal and Non Ideal IV Characteristics, CMOS devices, MOS(FET) Transistor Characteristic under Static and Dynamic Conditions, Technology Scaling, power consumption

1.1 INTRODUCTION TO VLSI

1.2 MOS Transistor nMOS and pMOS transistor

1.3 Modes of MOS TRANSISTOR

1.4 Operating regions of MOS transistor

1.5 IDEAL I-V CHARACTERISTICS OF MOS TRANSISTOR

1.6 C – V CHARACTERISTICS OF MOS TRANSISTOR (AC characteristics)

1.7 DC TRANSFER CHARACTERISTICS

1.8 NON IDEAL I-V EFFECTS

1.9 Device models

1.10 SCALING

1.11 CMOS DEVICES & TECHNOLOGIES

UNIT II - COMPUTATIONAL LOGIC CIRCUITS

Propagation Delays, stick diagram, Layout diagrams, Examples of combinational logic design, Elmore’s constant, Static Logic Gates, Dynamic Logic Gates, Pass Transistor Logic, Power Dissipation, Low Power Design principles

2.1 Delay estimation

2.1.1 RC Delay Model

2.2 Stick diagram

2.3 Layout Design Rules and Gate Layouts

2.4 Latchup problem

2.5 Introduction (Combinational Logic Circuit)

2.6  Elmore’s Delay

Logical effort

2.7 Pass Transistor

2.8 Transmission Gates

2.9 Cascaded CMOS Inverter

2.10 Circuit Families

Skewed gates

2.10.2 Ratioed Circuits

2.10.3 pseudo nMOS

2.10.4: Ganged capacitor

2.10.5 Differential Cascode voltage switch with pass gate logic (DCVSPG)

2.11:Dynamic CMOS design

2.12: Pass Transistor Logic

2.12.1: Differential Pass Transistor Logic / Complementary Pass Transistor Logic (CPL)

2.12.2 Double Pass Transistor Logic (DPL)

2.13: CMOS with transmission gates

2.14: Domino logic

2.15: Dual Rail Domino Logic

2.16: Keepers

2.16.1: Differential keeper

2.16.2: Secondary precharge devices

2.16.3: Charge sharing

2.16.4: NP and Zipper Domino

2.17: Power dissipation

2.17.1: Dynamic power

2.17.1.1:Sources of dynamic power dissipation

2.17.1.2: Low Power Design Principles / Reducing dynamic power dissipation

2.17.2: Static power

2.17.2.1:Sources of static power dissipation

2.17.2.2:Methods of reducing static power

2.18 Circuit Pitfalls

UNIT – III SEQUENTIAL LOGIC CIRCUITS AND CLOCKING STRATEGIES

Static Latches and Registers, Dynamic Latches and Registers, Pipelines, Non-bistable Sequential Circuits, Timing classification of Digital Systems, Synchronous Design, Self-Timed Circuit Design .

3.1 Static Latches and Registers

3.1.2 SR Flip-Flops

3.1.3 Multiplexer Based Latches:

3.1.4 Master-Slave Based Edge Triggered Register

3.1.5 Non-ideal clock signals:

3.1.6 Low-Voltage Static Latches

3.2 Dynamic Latches and Registers

3.2.1 Dynamic Transmission-Gate Based Edge-triggered Registers

3.2.2 C2MOS Dynamic Register

3.2.3 True Single-Phase Clocked Register (TSPCR)

3.3 Timing Issues

3.4 Pipelining

3.4.1 NORA-CMOS—A Logic Style for Pipelined Structures

3.4.2 Latch- vs. Register-Based Pipelines

3.5 Choosing a Clocking Strategy

3.5.1 Static sequencing element methodology

3.6 Synchronous and Asynchronous circuits-Timing issues

3.7 Clock-Distribution Techniques

3.8 Self-Timed Circuit Design

3.8.1 Self-Timed Logic : An Asynchronous Technique

3.8.2 A simple synchronizer

3.8.3 Communicating between asynchronous clock domains

3.8.4 Arbiter

3.8.5 Synchronous versus Asynchronous Design

3.9 Pulse Registers

3.10 Sense-Amplifier Based Registers

3.11 Schmitt Trigger

3.12 Multivibrator Circuits

3.13 Astable Sequential Circuits

UNIT – IV

INTERCONNECT, MEMORY ARCHITECTURE AND ARITHMETICCIRCUITS

4.1. Design of Data path circuits

4.2. Ripple Carry Adder

4.3. Carry Look Ahead Adder (CLA):

4.4. Manchester Carry Chain Adder

4.4.1. HIGH SPEED ADDERS

Carry Select Adder

4.5. ALUs (ACCUMULATOR)

4.6. MULTIPLIERS

4.7. DIVIDERS

4.8. SHIFT REGISTERS

4.9. SPEED AND AREA TRADE OFF

4.10 Memory Architecture and Memory Control Circuits

4.10.2 Memory Architecture and Building Blocks

4.10.3 Memory Core

4.10.3.2 Non-Volatile READ-WRITE Memory

4.10.3.3 RAM – Random Access Memory

4.10.3.3.3 CAM – Content Addressable or Associate Memory

4.11 Memory peripheral (control) Circuits:

4.12: Low Power Memory design

Programming technology used in FPGA

UV-Erasable programming:

Re-Programmable Devices Architecture (FPGA)

The structure of FPGA:

RE-PROGRAMMABLE DEVICE ARCHITECTURE

FPGA(PROGRAMMABLE ASIC )interconnect routing procedures (Architectures):

INTERCONNECT

CAPACITANCE INTERCONNECT PARAMETER

CAPACITANCE COUPLING/ CAPACITANCE COUPLING EFFECT

RESIINTERCONNECT MODELINGSTANCE 

INTERCONNECT PARAMETER

Lumped RC Model/ The Elmore Delay

Distributed RC line Model/ Distributed rc line Model:

RESISTIVE PARASITICS:

INDUCTIVE PARASITICS

UNIT V ASIC DESIGN AND TESTING

Introduction ASIC

5.1: Types of ASICs

5.1.1:Full-Custom ASICs

5.1.2: Semi-custom ASICs – Design

5.2: ASIC Design Flow / Cycle

5.3: ASIC Cell Libraries

5.4: Library-Cell Design

CMOS Testing

Introduction to test benches: