VLSI DESIGN Unit Wise 16 Marks Important Questions and Answers

VLSI AND CHIP DESIGN Important Questions

VLSI DESIGN Unit Wise 16 Marks Important Questions and Answers

Unit 1

1. INTRODUCTION: (VLSI)

2. Explain the basic concept of nMOS and pMOS transistor with relevant symbol

3. Explain the accumulation (Enhancement) mode, depletion layer and inversion layer of MOS transistor with diagram.

4. Draw the small signal model of device during cut-off, linear and saturation. (April 2018). Discuss the cutoff, linear and saturation region operation of MOS transistor. (Nov 2009).

5. Explain the three different types of modes of operation of pMOS transistor. 

6. IDEAL I-V CHARACTERISTICS OF MOS TRANSISTOR

7.  C – V CHARACTERISTICS OF MOS TRANSISTOR (AC characteristics)

8. MOS(FET) Transistor Characteristic under Static and Dynamic Conditions

9. Derive the noise margins for a CMOS inverter

10. Explain in detail about the non ideal I-V characteristics of a CMOS device. (MAY 2013). Explain channel length modulation and body effect. (Nov 2009, May 2013)

11. Explain in detail about effect and its effect in MOS device.

12. Explain the following: Device models and device characteristics.

13. Discuss the scaling principles and its limits.

14. CMOS DEVICES & TECHNOLOGIES

15. Explain the twin tub process with a neat diagram. 

Unit 2

1. Derive an expression for the rise time, fall time and propagation delay of a CMOS inverter.

2. Briefly explain about the RC delay model.

3. Explain about stick diagram in VLSI design.

4. Discuss in detail with a neat layout, the design rules for a CMOS inverter.

5. Discuss the orgin of latch up problems in CMOS circuits with necessary diagrams. Explain the remedial measures.

6. Introduction (Combinational Logic Circuit)

7. What is meant by Elmore’s delay and give expression for Elmore’s delay?

8. Obtain the logical effort and path efforts of the given circuit.

9. Write short notes on pass transistor

10. Write short notes on transmission gates (TG).

11. Derive the generalized expression for propagation delay of N-cascaded CMOS inverters if ‘N’ is even and if ‘N’ is odd.

12. Draw and explain the function of static CMOS.

13. Design a circuit described by the Boolean function Y=[A.(B+C)(D+E)]’using CMOS logic.

14. What is meant by skewed gate and give functions of skewed gate with schematic diagrams?

15. Realize the following function Y=(A+BC)D+E using static CMOS logic.

16. Write short notes on ratioed circuits.

17. Explain the detail about pseudo-nMOS gates with neat circuit diagram.

18. Implement NAND gate using pseudo- nMOS logic

19. Explain about DCVSL logic with suitable example. 

20. Describe the basic principle of operation of dynamic CMOS, domino and NP domino logic with neat diagrams.

21. Explain Pass transistor logic with neat sketches.

22. Discuss in detail the characteristics of CMOS Transmission gates.

23. Explain the domino logic families with neat diagrams.

24. Briefly discuss the signal integrity issues in dynamic design

25. Describe the basic principle of operation of NP domino logic

26. Derive an expression for dynamic power dissipation.

27. Explain various ways to minimize the static and dynamic power dissipation.

28. Describe how dynamic voltage scaling can reduce dynamic power dissipation.

29. Explain the keeper logic family with neat diagrams.

Unit 3

1. Discuss in detail various static latches and registers.

2. Design a d-latch using transmission gate.

3. Explain the operation of master-slave based edge triggered register. 

4. Discuss about the design of sequential dynamic circuits.

5. Explain the operation of True Single Phase Clocked Register.

6. Explain in detail about timing issues needed for a logic operation.

7. Analyze the impact of spatial variations of clock signal on edge-triggered sequential logic circuits

8. Explain in detail about pipelining structure needed for a logic operation.

9. Discuss about the NORA–CMOS structure.

10. Compare Latch and register based pipelines

11. Discuss about strategy required for choosing a clock signal.

12. Synchronous and Asynchronous circuits-Timing issues

13. Design a clock distribution network based on H tree model for 16 nodes.

14. Discuss about asynchronous design in logic design.

15. How do eliminates metastability problem in sequential circuit and explain?

16. Compare synchronous and asynchronous design.

17. Design the pulse registers suitable for sequential CMOS circuits.

18. Write short notes on Sense – Amplifier Based Registers.

19. Explain the circuit and working of CMOS implementation of Schmitt Trigger.

20. Explain about Monostable and Astable Sequential Circuits.

Unit 4

1. Discuss about data path circuits.

2. Draw the structure of ripple carry adder and explain its operation.

3. Explain the operation and design of Carry lookahead adder (CLA).

4. Discuss about Manchester Carry Chain Adder.

5. Discuss about different types of high speed adders.

6. Design a carry bypass adder and discuss its features.

7. Design a carry select adder and discuss its features.

8. Briefly discuss about ALUs (accumulators).

9. Explain the design and operation of 4 x 4 multiplier circuit. 

10. With suitable example and with detailed steps explain Radix-4 modified booth encoding for an 8-bit signed multiplier.

11. Explain in detail about the design and procedure for dividers.

12. Design 4 input and 4 output barrel shifter using NMOS logic.

13. Discuss the details about speed and area trade off.

14. Discuss Memory classification and its architecture and building blocks.

15. Discuss Memory core its types in detail.

16. Explain about static and dynamic RAM.

17. Explain about CAM.

18. Explain the memory architecture and its control circuits in detail.

19. Discuss about Low power memory design.

20. Discuss the different types of programming technology used in FPGA design.

21. Draw and explain the operation of metal-metal antifuse and EPROM transistor.

22. Find the reason for referring EPROM technology as floating gate avalanche MOS.

23. Explain the reprogrammable device architecture with neat diagrams.

24. Give short notes on FPGA interconnect routing procedures. 

Unit 5

1. Introduction of ASIC 

2. Explain about different types of ASICs with neat diagram

3. Explain the full custom ASICs.

4. Briefly explain the semi-custom Asics with its classification.

5. Explain gate array based ASICs with diagrams.

6. Explain the ASIC design flow with a neat diagram.

7. Explain the standard Cell libraries in ASIC.

8. Explain the important of Library –cell design in detail.

9. Explain about Microchip design process.

10. Explain the Issues in Test and Verification of Complex Chips, Embedded Cores, and SoCs

11. 1. Explain the following: 

(i) Silicon debug principles.

12. Explain the manufacturing test principles in detail.

13. Explain with diagram the design strategies for testing the CMOS devices.

14. Describe the adhoc testing to design for testability in detail.

15. Explain in detail Scan based test techniques.

16. Explain Built in self-test.

17. Explain how to detect a stuck at fault with examples

18. Explain the system level test techniques. 

19. Explain the Writing test benches in Verilog HDL

20. Explain about Automatic Test Pattern Generation

21. Explain the Process involved in wafer to chip fabrication

1. Derive the CMOS inverter DC characteristics and obtain the relationship for output voltage at different region in the transfer characteristics.
2. Explain with neat diagrams the various CMOS fabrication technology
3. Explain the latch up prevention techniques.
4. Explain the operation of PMOS Enhancement transistor
5. Explain the silicon semiconductor fabrication process.
6. Explain various CAD tool sets.
7. Explain the latch up prevention techniques.
8. Explain the operation of PMOS Enhancement transistor
9. Explain the threshold voltage equation
10. Explain the silicon semiconductor fabrication process.
11. Explain the operation of NMOS Enhancement transistor.
12. Explain the Transmission gate and the tristate inverter briefly.
13. Explain about the various non ideal conditions in MOS device model.
14. Explain the design hierarchies.
15. Explain the concept of MOSFET as switches
16. Explain the ASIC design flow with a neat diagram
17. Explain the concept of Delay estimation, logical effort and sizing of MOSFET.
18. Explain fault models.
A) Stuck-At Faults
B) Explain ATPG.
19. Briefly explain
a) Fault grading & fault simulation
b) Delay fault testing
c) Statistical fault analysis
20. Explain scan-based test techniques.
21. Explain Ad-Hoc testing and chip level test techniques.
22. Explain self-test techniques and IDDQ testing.
23. Explain system-level test techniques.
24. Explain the concept involved in Timing control in VERILOG.
25. Explain with neat diagrams the Multiplexer and latches using transmission Gate.
26. Explain the concept of gate delay in VERILOG with example
27. Explain the concept of MOSFET as switches and also bring the various logic gates using the switching concept.
28. Explain the concept involved in structural gate level modeling and also give the
description for half adder and Full adder.
29. What is ASIC? Explain the types of ASIC.
30. Explain the VLSI design flow with a neat diagram.

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